<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Low Latency on Mechanical Snail</title><link>https://mechanicalsnail.com/tags/low-latency/</link><description>Recent content in Low Latency on Mechanical Snail</description><image><title>Mechanical Snail</title><url>https://mechanicalsnail.com/images/logo.png</url><link>https://mechanicalsnail.com/images/logo.png</link></image><generator>Hugo -- 0.152.2</generator><language>en-us</language><lastBuildDate>Mon, 02 Sep 2024 10:00:00 +0100</lastBuildDate><atom:link href="https://mechanicalsnail.com/tags/low-latency/index.xml" rel="self" type="application/rss+xml"/><item><title>Low-Latency Trading Systems in Rust</title><link>https://mechanicalsnail.com/posts/low-latency-trading-rust/</link><pubDate>Mon, 02 Sep 2024 10:00:00 +0100</pubDate><guid>https://mechanicalsnail.com/posts/low-latency-trading-rust/</guid><description>Engineering microsecond-latency trading systems in Rust: lock-free data structures, cache-line optimization, kernel bypass networking, and hot paths that never allocate.</description></item><item><title>Vector Optimization: SIMD, Cache Lines &amp; Memory Bandwidth</title><link>https://mechanicalsnail.com/posts/vector-optimization-simd/</link><pubDate>Fri, 11 Mar 2022 10:00:00 +0100</pubDate><guid>https://mechanicalsnail.com/posts/vector-optimization-simd/</guid><description>Why vector code is memory-bound, not compute-bound: cache-line behaviour, array-of-structs versus struct-of-arrays layout, AVX vectorization, and the bandwidth ceiling.</description></item></channel></rss>